| 引用本文: | 周宏伟,徐实,王忠奕,等.众核处理器访存链路接口的FPGA验证.[J].国防科技大学学报,2018,40(3):176-182.[点击复制] |
| ZHOU Hongwei,XU Shi,WANG Zhongyi,et al.FPGA verification for memory link interface of many-core processor[J].Journal of National University of Defense Technology,2018,40(3):176-182[点击复制] |
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| 众核处理器访存链路接口的FPGA验证 |
| 周宏伟1, 徐实2, 王忠奕1, 杨乾明1, 冯权友1, 邓让钰1, 窦强1 |
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(1. 国防科技大学 计算机学院， 湖南 长沙 410073;2. 湖南大学 信息科学与工程学院， 湖南 长沙 410082)
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| 摘要: |
| 面向众核处理器提出一种访存链路接口的现场可编程门阵列（Field-Programmable Gate Array, FPGA）验证平台，用于对处理器访存链路关键部件进行功能及可靠性测试。提出片上读写激励自动产生与检查机制、以太网接口硬件用户数据报协议(User Datagram Protocol, UDP)协议栈和FPGA芯片间多通道并行链路三项关键技术并进行设计实现。实验结果表明提出的各项关键技术功能正确，不仅丰富了功能验证中随机激励产生及结果验证的手段，而且实现了对链路数据检错和多lane间延迟偏斜纠正逻辑的可靠性测试与评估。经过该平台验证的访存链路接口在实际芯片中通过了功能正确性测试，证明了验证的有效性。 |
| 关键词: 众核处理器 访存 链路 现场可编程门阵列 验证 |
| DOI：10.11887/j.cn.201803027 |
| 投稿日期：2016-12-31 |
| 基金项目:国家自然科学基金资助项目（61303069，61472432，61602498）；核高基重大专项基金资助项目（2015ZX01028101） |
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| FPGA verification for memory link interface of many-core processor |
| ZHOU Hongwei1, XU Shi2, WANG Zhongyi1, YANG Qianming1, FENG Quanyou1, DENG Rangyu1, DOU Qiang1 |
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(1. College of Computer, National University of Defense Technology, Changsha 410073, China;2. College of Computer Science and Electronic Engineering, Hunan University, Changsha 410082, China)
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| Abstract: |
| An FPGA(field-programmable gate array) verification platform for memory link interface of many core processor was proposed to test the function and reliability of the main components of the processor′s memory access link. Three key technologies, the on-chip read-write requests automatic generation and result checking mechanism, the hardware UDP(user datagram protocol) protocol stack in Ethernet interface and the multi-lane parallel link between FPGA chips were proposed and implemented. Experiments on the platform show that the proposed technologies are correct, they not only enrich the ways of the random request generation and result checking for functional verification, but also can test and evaluate the logics of link errors detection and lane to lane deskew. The proposed platform has been used to verify a real many-core processor in which the function of memory link interface is correct, so the validity of the verification is proved. |
| Keywords: many-core processor memory access link field-programmable gate array verification |
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