| 引用本文: | 鲁建壮,孙书为,陈胜刚,等.采用S-Tag的M-DSP片上存储DMA访问优化.[J].国防科技大学学报,2018,40(6):112-117.[点击复制] |
| LU Jianzhuang,SUN Shuwei,CHEN Shenggang,et al.S-Tag based DMA optimization for on-chip memory in M-DSP[J].Journal of National University of Defense Technology,2018,40(6):112-117[点击复制] |
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| 采用S-Tag的M-DSP片上存储DMA访问优化 |
| 鲁建壮1, 孙书为1, 陈胜刚1, 陆文远2 |
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(1. 国防科技大学 计算机学院， 湖南 长沙 410073;2. 西安卫星测控中心， 陕西 西安 710043)
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| 摘要: |
| 针对自主设计的M-DSP，提出并设计实现了一种基于Tag副本(S-Tag)的片上SRAM DMA访问数据相关性维护机制，该机制以流水化方式实现，在基本对CPU无打扰的前提下，有效支撑了DMA数据的无阻塞传递。仿真和芯片实测结果表明，该机制硬件开销较小，并在有效带宽和带宽利用率上均优于已有典型同类芯片。 |
| 关键词: Cache+RAM结构 S-Tag DMA传输 数据一致性 |
| DOI：10.11887/j.cn.201806015 |
| 投稿日期：2017-09-16 |
| 基金项目:国家自然科学基金资助项目（61402499,61402500,61602493） |
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| S-Tag based DMA optimization for on-chip memory in M-DSP |
| LU Jianzhuang1, SUN Shuwei1, CHEN Shenggang1, LU Wenyuan2 |
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(1. College of Computer, National University of Defense Technology, Changsha 410073, China;2. Xi′an Satellite Control Center, Xi′an 710043, China)
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| Abstract: |
| The S-Tag (Shadow Tag) mechanism of SRAM(static random access memory) data consistency maintaining for DMA(direct memory access) accessing was proposed for the independent design of M DSP(multi-core digital signal processor). The pipelining implementation can efficiently support DMA non blocking data transfer, and release the CPU. Experimental results and tests in real chips show that the proposed mechanism outperforms the state-of-art ones with respect to bandwidth and bandwidth utilization while keeping relatively lower hardware cost. |
| Keywords: Cache+RAM structure S-Tag DMA data transfer data coherence |
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