| 引用本文: | 孙鹏跃,吕晟莱,毛二坤,等.利用整帧翻转的SRAM型FPGA故障注入加速算法.[J].国防科技大学学报,2023,45(5):207-211.[点击复制] |
| SUN Pengyue,LYU Shenglai,MAO Erkun,et al.Accelerated fault injection algorithm for SRAM-based FPGA using whole frame upset[J].Journal of National University of Defense Technology,2023,45(5):207-211[点击复制] |
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| 利用整帧翻转的SRAM型FPGA故障注入加速算法 |
| 孙鹏跃,吕晟莱,毛二坤,张书政,陈雷,周欢,黄仰博,楼生强 |
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(国防科技大学 电子科学学院, 湖南 长沙 410073)
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| 摘要: |
| 不可恢复异常比特位(unrecoverable-sensitive bits, UR-SB)不能通过定时刷新修复,会造成卫星载荷在轨服务的长时间中断,是地面故障注入试验需要着重评估和改善的。但UR-SB占比极低,若采用传统逐位翻转故障注入方法,其测试耗时太长,效率极低。提出了一种基于整帧翻转的静态随机存取存储器型现场可编程门阵列的故障注入加速算法,其通过整帧翻转能够快速筛除不存在UR-SB的配置帧,并进一步用二分法对存在UR-SB的配置帧进行快速搜索,有效加速了UR-SB的精确定位过程。以在轨常用XQR2V3000器件为例,理论分析在较差情况下测试效率可提升207倍,信号生成载荷实测结果最高可提升949倍,理论分析和实测结果均验证了所提加速算法的有效性。 |
| 关键词: 故障注入 整帧翻转 不可恢复异常比特位 抗辐照可靠性 现场可编程门阵列 |
| DOI：10.11887/j.cn.202305024 |
| 投稿日期：2021-07-16 |
| 基金项目:国家自然科学基金资助项目(62201585)；湖南省科技创新计划资助项目(2023RC3004) |
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| Accelerated fault injection algorithm for SRAM-based FPGA using whole frame upset |
| SUN Pengyue, LYU Shenglai, MAO Erkun, ZHANG Shuzheng, CHEN Lei, ZHOU Huan, HUANG Yangbo, LOU Shengqiang |
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(College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China)
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| Abstract: |
| UR-SB (unrecoverable-sensitive bits), which cannot be corrected by regular refresh, will cause long-term interruption of on-orbit service of satellite load. Thus, the impact of UR-SB needs to be evaluated and improved deeply by the fault injection tests. However, the proportion of UR-SB is extremely low. If the traditional bit-by-bit upset fault injection method is adopted, the fault injection tests would take too long time, and the efficiency is extremely low. A fault injection acceleration algorithm for static random access memory-based field programmable gate array based on whole frame upset was proposed, which can quickly filter out the configuration frames without UR-SB through whole frame upset fault injection. By taking dichotomy on the configuration frames with UR-SB, the precise positioning process of UR-SB can be speeded up effectively. Taking the commonly used XQR2V3000 device as an example, the simulation results indicate that the test efficiency can be improved by 207 times under the poor conditions, and the real data experimental results of the signal generation load by our group are increased by 949 times. These results demonstrate the validity of the acceleration algorithm proposed in this article. |
| Keywords: fault injection whole frame upset UR-SB reliability of anti-irradiation FPGA |
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