引用本文: | 郑静雅,安军社.轻量级SpaceFibre节点高速传输系统的优化设计[J].国防科技大学学报,2024,46(2):104-114.[点击复制] |
ZHENG Jingya,AN Junshe.Optimal design for the high-speed and lightweight transmission system of SpaceFibre node[J].Journal of National University of Defense Technology,2024,46(2):104-114[点击复制] |
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轻量级SpaceFibre节点高速传输系统的优化设计 |
郑静雅1,2,安军社1 |
(1. 中国科学院国家空间科学中心 复杂航天系统电子信息技术重点实验室, 北京 100190;2. 中国科学院大学 计算机科学与技术学院, 北京 100049)
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摘要: |
为满足卫星有效载荷间SpaceFibre链路的高带宽、高可靠性和轻量化的应用需求,提出一种SpaceFibre节点传输系统的优化设计。该设计采用基于帧累计的增量化计算方法减少了计算电路的冗余;通过四级流水架构满足了错误检测操作的时序要求,使用循环冗余校验共享机制平衡了硬件资源的使用;采取基于完整应答的双层控制策略提升了系统的可靠性,通过构建面向资源优化的控制状态机和存储架构简化了确认重传算法的实现逻辑。使用型号为XC7Z100FFG900-2的FPGA搭建双节点系统,板级验证表明:该设计满足协议规范,与同类设计方案相比,最高工作频率提高1.5倍,支持最高6.25 Gbit/s的传输速率,查找表资源和存储资源降低,寄存器资源相近,为开发具有自主知识产权的高速可靠SpaceFibre编解码器提供了参考。 |
关键词: 超高速SpaceFibre 现场可编程门阵列 性能优化 错误恢复 服务质量 |
DOI:10.11887/j.cn.202402011 |
投稿日期:2021-12-02 |
基金项目:中国科学院战略性先导科技专项基金资助项目(XDA15020205) |
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Optimal design for the high-speed and lightweight transmission system of SpaceFibre node |
ZHENG Jingya1,2, AN Junshe1 |
(1. Key Laboratory of Electronics and Information Technology for Space Systems, National Space Science Center, Chinese Academy of Sciences, Beijing 100190, China;2. School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049, China)
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Abstract: |
An optimal design of SpaceFibre node transmission system was proposed to meet the high bandwidth, high reliability and light weight requirements for the SpaceFiber link between satellite payloads. This design adopts an incremental calculation method based on frame accumulation to reduce the redundancy of computing circuits, and satisfies the timing requirements for error detection operations through a four-stage pipeline architecture. The module balances the use of hardware resources by sharing CRC(cyclic redundancy check). To improve reliability, the design adopts a two-layer control strategy with complete response. Resource-optimized FSM(finite-state machine) and storage architecture are built to simplify the implementation of the retransmission algorithm. A verification system at board-level with two nodes was implemented in XC7Z100FFG900-2 FPGA(field programmable gate array). The results show that the design satisfies the functions stipulated by the standard. Compared with similar design schemes, the maximum frequency is increased by 1.5 times, and supports up to 6.25 Gbit/s transmission rate. And resources of lookup tables and storage are reduced, while register resources are similar. The design provides a reference for the development of high-speed and reliable SpaceFibre codecs with independent intellectual property rights. |
Keywords: high-speed SpaceFibre FPGA performance optimizing error recovery quality of service |
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