Rolling cyclic redundancy code (Rolling CRC) uses two generator polynomials for code generation. The degree of error detection capability provided by current implementations is not strong enough to check missing of a whole packet in a series of identical ones. A modified Rolling CRC, named MR-CRC, was presented for the data error checking, which adopted higher degree polynomials, chose the proper combination and revised the schemes used in original generator and detector. The result of FPGA implementation shows that this method has low logic complexity, can improve error detection and provide advanced reliability with little performance depression. Compared with the FPGA results of 16B rolling CRC and traditional 32B CRC, the former can improve the frequency by 25% with 10% less LUTs.