With the development of the high performance servers and very large scale super computers, the requirement for board-level high-speed data transportation bus is higher than before. How to reduce the transfer delay between chips and improve the ratio of computation to communication is very important. In light of this, the characteristics of link layer in Hyper Transport and PCI Express buses which are very popular in recent years was studied. On the basis of this, link layer architecture for a 64-bit high-speed data transportation bus was proposed and some key technologies were researched. A 16-bit scrambler/descrambler, which can scramble or descramble a 16-bit data in one cycle, was designed. A lane-to-lane deskew logic, which can correct 5 cycles delay skews at most between two lanes, was also proposed. The verification results show that the function of our designs is correct.