In the traditional Network-on-Chip routers, packets from different directions are temporarily stored in different buffer regions, and these buffering resources are independent from each other. Under non-uniform traffic patterns, buffers in some input channel will be crammed by the coming packets quickly, while the others are still in idle state. As a result, the buffers are utilized inefficiently, and it has a negative influence on the overall network performance. In the method proposed, an adaptive buffer regulating scheme that can be used to achieve similar performance by using less buffering resources was introduced. The VLSI implementation of a router with the buffer regulating scheme was completed under 90nm CMOS process. The experimental results show that the proposed router can bring significant performance improvement and power reduction under non-uniform traffic patterns, 20.3% area saving of the proposed router and 41% power reduction of the buffers can be achieved compared to the traditional one.