The encoding algorithms of the LDPC codes with quasi-cyclic dual-diagonal parity check matrix were studied. It is demonstrated that the matrix decomposition encoding algorithm and the cumulative recursion encoding algorithm are equivalent for implementation. The cumulative recursion encoding algorithm is straightforwardly facilitated to hardware implementation. Besides, a partly parallel encoding architecture for the QC-LDPC codes with dual-diagonal parity check matrix was proposed and a LDPC encoder compatible with IEEE 802.11n standard was designed. FPGA implementation results show that the hardware overhead of the proposed LDPC encoder is low and the throughput is high. The encoding throughput can reach up to 13Gbps with code length 1944-bit and rate 5/6.