Recomputation and correction mechanism design for tagged instructions of the RISC-V core
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(College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China)

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TP302.8

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    Abstract:

    The reliability of the computer system is significantly compromised by the hardware transient faults which are mainly caused by the cosmic radiation and other environmental factors. To mitigate this undesirable impact and guarantee the correctness of the running programs, a recomputation and correction mechanism for tagged instructions for an open source core named “Humming bird e203”, which is based on the RISC-V instruction set architecture, was proposed. This mechanism adds extra flag bits for each instruction and thus enables flexible recomputation for any tagged instruction at low hardware cost. Besides, it can issue the tagged instruction again automatically if the result of the first recomputation is different from the original one. This majority voting scheme can efficiently rectify most data flow errors caused by transient hardware faults. The experimental results show that with our proposal and the interrupt handler, the average probability at which programs can operate correctly can be increased by 86.67% under the random transient fault insertion.

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DENG Ding, GUO Yang. Recomputation and correction mechanism design for tagged instructions of the RISC-V core[J]. Journal of National University of Defense Technology,2020,42(6):90-97.

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History
  • Received:June 13,2019
  • Revised:
  • Adopted:
  • Online: December 02,2020
  • Published: December 28,2020
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