[cn_name]
[cn_description]
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[en_acquisition_editor]
2023, 45(1):1-14.
DOI: 10.11887/j.cn.202301001
Abstract:
In order to master the current development status and development trends of memristor based neuromorphic chips, the existing memristor based neuromorphic chips and architectures were investigated. The memristor array structure and integration process, anterior and posterior neuron circuits, multi-array interconnection topology and data transmission strategy used in the chip, as well as the system simulation and evaluation methods used in the chip design process were compared and analyzed. It is concluded that the current circuit design of memristor based neuromorphic chips still need to solve the problems of limited resistance states, large device parameter fluctuation, complex array peripheral circuits, small integration scale, etc. It is pointed out that the actual application of this type of chip still faces challenges such as the improvement of memristor production process, improvement of development tool support, special instruction set development, and determination of typical traction applications.
In order to master the current development status and development trends of memristor based neuromorphic chips, the existing memristor based neuromorphic chips and architectures were investigated. The memristor array structure and integration process, anterior and posterior neuron circuits, multi-array interconnection topology and data transmission strategy used in the chip, as well as the system simulation and evaluation methods used in the chip design process were compared and analyzed. It is concluded that the current circuit design of memristor based neuromorphic chips still need to solve the problems of limited resistance states, large device parameter fluctuation, complex array peripheral circuits, small integration scale, etc. It is pointed out that the actual application of this type of chip still faces challenges such as the improvement of memristor production process, improvement of development tool support, special instruction set development, and determination of typical traction applications.
2023, 45(5):202-206.
DOI: 10.11887/j.cn.202305023
Abstract:
Memristor based neuromorphic computing architecture has achieved good results in image classification, speech recognition and other fields, but when the memristor array has the problem of low yield, the performance declines significantly. A method combining memristive neuromorphic computing based calibration method with in-situ training was proposed, which increased the accuracy of multiplicative accumulation calculation by using the calibration method and reduced the training error by using the in-situ training method. In order to verify the performance of the proposed method, a multi-layer perceptron architecture was used for simulation. From the simulation results, the accuracy of the neural network is improved obviously (nearly 40%). Experimental results show that compared with the single calibration method, the precision of the network trained by the proposed method is improved by about 30%, and the precision of the network trained by the proposed method is improved by 0.29% when compared with other mainstream methods.
Memristor based neuromorphic computing architecture has achieved good results in image classification, speech recognition and other fields, but when the memristor array has the problem of low yield, the performance declines significantly. A method combining memristive neuromorphic computing based calibration method with in-situ training was proposed, which increased the accuracy of multiplicative accumulation calculation by using the calibration method and reduced the training error by using the in-situ training method. In order to verify the performance of the proposed method, a multi-layer perceptron architecture was used for simulation. From the simulation results, the accuracy of the neural network is improved obviously (nearly 40%). Experimental results show that compared with the single calibration method, the precision of the network trained by the proposed method is improved by about 30%, and the precision of the network trained by the proposed method is improved by 0.29% when compared with other mainstream methods.
TANG Liqin
,
DIAO Jietao
,
CHEN Changlin
,
LUO Changhang
,
LIU Biao
,
LIU Sitong
,
ZHANG Yufei
,
WANG Qin
2023, 45(5):222-230.
DOI: 10.11887/j.cn.202305026
Abstract:
To address the problems of inefficient data loading and readout and poor flexibility of array collaboration in existing multi-memristor-array, a highly efficient and flexible multi-array interconnection architecture was proposed. The data loading strategy of the architecture supports data reuse in multiple weight mapping modes, reducing the need for off-chip data access; the readout network supports flexible combination of multiple processing units to achieve different scales of convolutional operations, as well as fast accumulation and readout of computation results, thus improving chip flexibility and overall computing power. Simulation experiments performed on the NeuroSim platform with running VGG-8 networks indicate a 146% increase in processing speed than that of the MAX2 neural network accelerator, with only a 6% increase in area overhead.
To address the problems of inefficient data loading and readout and poor flexibility of array collaboration in existing multi-memristor-array, a highly efficient and flexible multi-array interconnection architecture was proposed. The data loading strategy of the architecture supports data reuse in multiple weight mapping modes, reducing the need for off-chip data access; the readout network supports flexible combination of multiple processing units to achieve different scales of convolutional operations, as well as fast accumulation and readout of computation results, thus improving chip flexibility and overall computing power. Simulation experiments performed on the NeuroSim platform with running VGG-8 networks indicate a 146% increase in processing speed than that of the MAX2 neural network accelerator, with only a 6% increase in area overhead.
2022, 44(5):80-91.
DOI: 10.11887/j.cn.202205009
Abstract:
Reduction and scan are two critical primitives in parallel computing. Thus, accelerating reduction and scan shows great importance. However, the Von Neumann architecture suffers from performance and energy bottlenecks known as “memory wall” due to the unavoidable data migration. Recently, NVM (non-volatile memory) such as ReRAM (resistive random access memory), enables in-situ computing without data movement and its crossbar architecture can perform parallel GEMV (matrix-vector multiplication) operation naturally in one step. ReRAM-based architecture has demonstrated great success in many areas, e.g. accelerating machine learning and graph computing applications, etc. Parallel acceleration methods were proposed for reduction and scan primitives on ReRAM-based PIM(processing in memory) architecture, the computing process in terms of GEMV and the mapping method on the ReRAM crossbar were focused, and the co-design of software and hardware was realized to reduce power consumption and improve performance. Compared with GPU, the proposed reduction and scan algorithm achieved substantial speedup by two orders of magnitude, and the average acceleration ratio can also reach two orders of magnitude. The case of segmentation can achieve up to five (four on average) orders of magnitude. Meanwhile, the power consumption decreased by 79%.
Reduction and scan are two critical primitives in parallel computing. Thus, accelerating reduction and scan shows great importance. However, the Von Neumann architecture suffers from performance and energy bottlenecks known as “memory wall” due to the unavoidable data migration. Recently, NVM (non-volatile memory) such as ReRAM (resistive random access memory), enables in-situ computing without data movement and its crossbar architecture can perform parallel GEMV (matrix-vector multiplication) operation naturally in one step. ReRAM-based architecture has demonstrated great success in many areas, e.g. accelerating machine learning and graph computing applications, etc. Parallel acceleration methods were proposed for reduction and scan primitives on ReRAM-based PIM(processing in memory) architecture, the computing process in terms of GEMV and the mapping method on the ReRAM crossbar were focused, and the co-design of software and hardware was realized to reduce power consumption and improve performance. Compared with GPU, the proposed reduction and scan algorithm achieved substantial speedup by two orders of magnitude, and the average acceleration ratio can also reach two orders of magnitude. The case of segmentation can achieve up to five (four on average) orders of magnitude. Meanwhile, the power consumption decreased by 79%.
